diff --git a/X10D/src/Core/IntrinsicUtility.cs b/X10D/src/Core/IntrinsicUtility.cs
index 6776bbc..f064124 100644
--- a/X10D/src/Core/IntrinsicUtility.cs
+++ b/X10D/src/Core/IntrinsicUtility.cs
@@ -17,6 +17,8 @@ public static class IntrinsicUtility
// ANYTHING OPERATION OPERATION ON ANYTHING THAT ISN'T FLOAT IS NOT SSE COMPATIBLE, MUST BE SSE2 AND BEYOND VERSION
// FOR API CONSISTENCY.
+ // TODO: Fallback? No idea if it is worth it since even CPU made from before 2000 support SSE and SSE2.
+
///
///
Correcting of into 0 and 1 depend on their boolean truthiness.
///
Operation (raw):
@@ -33,8 +35,9 @@ public static class IntrinsicUtility
///
///
/// Vector of byte to correct.
- ///
+ /// A of which remapped back to 0 and 1 based on boolean truthiness.
/// API avaliable on ARM NEON (untested) hardware.
+ /// Hardware doesn't suppot ARM NEON intrinsic set.
[Pure]
[MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)]
public static Vector64 CorrectBoolean(Vector64 vector)
@@ -47,12 +50,14 @@ public static class IntrinsicUtility
return result;
}
- if (Sse.IsSupported)
+
+ // No comparison, bitwise AND with 64-bit vector on SSE and beyond.
+ if (Sse2.IsSupported)
{
- throw new PlatformNotSupportedException("Cannot correct boolean of Vector64 on SSE intrinsic set.");
+ throw new PlatformNotSupportedException("Operation is not supported on SSE2 instruction set.");
}
- throw new PlatformNotSupportedException("Unknown Intrinsic platform.");
+ throw new PlatformNotSupportedException("Unknown intrinsic instruction set.");
}
///
@@ -71,8 +76,9 @@ public static class IntrinsicUtility
///
///
/// Vector of byte to correct.
- ///
+ /// A of which remapped back to 0 and 1 based on boolean truthiness.
/// API avaliable on SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, ARM NEON (untested) hardwares.
+ /// Hardware doesn't support ARM NEON or SSE2 instruction set.
[Pure]
[MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)]
public static Vector128 CorrectBoolean(Vector128 vector)
@@ -93,7 +99,7 @@ public static class IntrinsicUtility
return result;
}
- throw new PlatformNotSupportedException("Unknown Intrinsic platform.");
+ throw new PlatformNotSupportedException("Unknown intrinsic instruction set.");
}
///
@@ -112,8 +118,9 @@ public static class IntrinsicUtility
///
///
/// Vector of byte to correct.
- ///
+ /// A of which remapped back to 0 and 1 based on boolean truthiness.
/// API avaliable on AVX2 hardware.
+ /// Hardware doesn't support AVX2 instruction set.
[Pure]
[MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)]
public static Vector256 CorrectBoolean(Vector256 vector)
@@ -125,12 +132,13 @@ public static class IntrinsicUtility
return result;
}
+
if (AdvSimd.IsSupported)
{
- throw new PlatformNotSupportedException("Cannot correct boolean of Vector256 on ARM intrinsic set.");
+ throw new PlatformNotSupportedException("Operation is not supported on ARM NEON instruction set.");
}
- throw new PlatformNotSupportedException("Unknown Intrinsic platform.");
+ throw new PlatformNotSupportedException("Unknown intrinsic instruction set.");
}
///
@@ -143,8 +151,9 @@ public static class IntrinsicUtility
///
/// Left vector.
/// Right vector.
- ///
+ /// A of whose elements is 64-bit truncated product of lhs and rhs.
/// API avaliable on SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, ARM NEON (untested) hardwares.
+ /// Hardware doesn't support SSE2 or ARM NEON instruction set.
[Pure]
[CLSCompliant(false)]
[MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)]
@@ -192,8 +201,9 @@ public static class IntrinsicUtility
///
/// Left vector.
/// Right vector.
- ///
+ /// A of whose elements is 64-bit truncated product of lhs and rhs.
/// API avaliable on AVX2 hardware.
+ /// Hardware doesn't support AVX2 instruction set.
[Pure]
[CLSCompliant(false)]
[MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)]
@@ -227,8 +237,9 @@ public static class IntrinsicUtility
///
/// Left vector.
/// Right vector.
- ///
+ /// A of whose elements is 64-bit truncated product of lhs and rhs.
/// API avaliable on SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, ARM NEON (untested) hardwares.
+ /// Hardware doesn't support SSE2 or ARM NEON instruction set.
[Pure]
[MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)]
public static Vector128 Multiply(Vector128 lhs, Vector128 rhs)
@@ -248,8 +259,9 @@ public static class IntrinsicUtility
///
/// Left vector.
/// Right vector.
- ///
+ /// A of whose elements is 64-bit truncated product of lhs and rhs.
/// API avaliable on AVX2 hardware.
+ /// Hardware doesn't support AVX2 instruction set.
[Pure]
[MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)]
public static Vector256 Multiply(Vector256 lhs, Vector256 rhs)
@@ -269,8 +281,9 @@ public static class IntrinsicUtility
///
/// Left vector.
/// Right vector.
- ///
+ /// A of with all elements is result of OR operation on adjacent pairs of elements in lhs and rhs.
/// API avaliable on SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, ARM64 NEON (untested) hardwares.
+ /// Hardware doesn't support ARM64 NEON or SSE instruction set.
[Pure]
[MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)]
public static Vector128 HorizontalOr(Vector128 lhs, Vector128 rhs)
@@ -306,8 +319,9 @@ public static class IntrinsicUtility
///
/// Left vector.
/// Right vector.
- ///
+ /// A of with all elements is result of OR operation on adjacent pairs of elements in lhs and rhs.
/// API avaliable on SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, ARM64 NEON (untested) hardwares.
+ /// Hardware doesn't support ARM64 NEON or SSE instruction set.
[Pure]
[MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)]
public static Vector128 HorizontalOr(Vector128 lhs, Vector128 rhs)
@@ -327,8 +341,9 @@ public static class IntrinsicUtility
///
/// Left vector.
/// Right vector.
- ///
+ /// A of with all elements is result of OR operation on adjacent pairs of elements in lhs and rhs.
/// API avaliable on SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, ARM64 NEON (untested) hardwares.
+ /// Hardware doesn't support ARM64 NEON or SSE2 instruction set.
[Pure]
[MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)]
[CLSCompliant(false)]
@@ -347,8 +362,9 @@ public static class IntrinsicUtility
///
///
/// Input vector.
- ///
+ /// A of with elements the same as input vector except their positions/indices are reversed.
/// API available on SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 hardwares.
+ /// Hardware doesn't support SSE2 instruction set.
[Pure]
[CLSCompliant(false)]
[MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)]
diff --git a/X10D/src/Core/SpanExtensions.cs b/X10D/src/Core/SpanExtensions.cs
index a12e4bb..52da227 100644
--- a/X10D/src/Core/SpanExtensions.cs
+++ b/X10D/src/Core/SpanExtensions.cs
@@ -112,9 +112,9 @@ public static class SpanExtensions
default:
#if NET7_0_OR_GREATER
throw new UnreachableException($"Enum with the size of {Unsafe.SizeOf()} bytes is unexpected.");
-#else
+#else // NET7_0_OR_GREATER
throw new ArgumentException($"Enum with the size of {Unsafe.SizeOf()} bytes is unexpected.");
-#endif
+#endif // NET7_0_OR_GREATER
}
#pragma warning restore CS8500 // This takes the address of, gets the size of, or declares a pointer to a managed type
}