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103
X10D.Tests/src/Core/SpanTest.cs
Normal file
103
X10D.Tests/src/Core/SpanTest.cs
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@ -0,0 +1,103 @@
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using Microsoft.VisualStudio.TestTools.UnitTesting;
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using X10D.Collections;
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using X10D.Core;
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namespace X10D.Tests.Core;
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[TestClass]
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public class SpanTest
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{
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[TestMethod]
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public void Pack8Bit_Should_Pack_Correctly()
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{
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Span<bool> span = stackalloc bool[8] { true, true, false, false, true, true, false, false };
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Assert.AreEqual(0b00110011, span.PackByte());
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}
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[TestMethod]
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public void Pack8Bit_Should_Pack_Correctly_Randomize()
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{
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var value = new Random().NextByte();
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Span<bool> unpacks = stackalloc bool[8];
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value.Unpack(unpacks);
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Assert.AreEqual(value, unpacks.PackByte());
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}
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[TestMethod]
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public void Pack16Bit_Should_Pack_Correctly()
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{
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ReadOnlySpan<bool> span = stackalloc bool[16] {
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false, false, true, false, true, false, true, true,
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true, false, true, true, false, true, false, false,
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};
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Assert.AreEqual(0b00101101_11010100, span.PackInt16());
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}
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[TestMethod]
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public void Pack16Bit_Should_Pack_Correctly_Randomize()
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{
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var value = new Random().NextInt16();
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Span<bool> unpacks = stackalloc bool[16];
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value.Unpack(unpacks);
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Assert.AreEqual(value, unpacks.PackInt16());
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}
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[TestMethod]
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public void Pack32Bit_Should_Pack_Correctly()
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{
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ReadOnlySpan<bool> span = stackalloc bool[] {
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false, true, false, true, false, true, false, true,
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true, false, true, false, true, false, true, false,
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false, true, false, true, false, true, false, true,
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true, false, true, false, true, false, true, false,
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};
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Assert.AreEqual(0b01010101_10101010_01010101_10101010, span.PackInt32());
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}
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[TestMethod]
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public void Pack32Bit_Should_Pack_Correctly_Randomize()
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{
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var value = new Random().Next(int.MinValue, int.MaxValue);
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Span<bool> unpacks = stackalloc bool[32];
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value.Unpack(unpacks);
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Assert.AreEqual(value, unpacks.PackInt32());
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}
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[TestMethod]
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public void Pack64Bit_Should_Pack_Correctly()
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{
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ReadOnlySpan<bool> span = stackalloc bool[] {
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true, false, true, false, false, true, false, true,
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false, false, true, true, false, true, false, false,
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true, true, true, false, true, false, false, true,
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false, true, false, false, true, false, false, false,
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false, true, true, false, true, false, true, true,
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true, false, false, true, false, true, true, false,
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false, true, true, false, true, false, true, true,
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true, false, true, false, true, false, true, false,
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};
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Assert.AreEqual(0b01010101_11010110_01101001_11010110_00010010_10010111_00101100_10100101, span.PackInt64());
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}
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[TestMethod]
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public void Pack64Bit_Should_Pack_Correctly_Randomize()
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{
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var rand = new Random();
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long value = ((long)rand.Next() << 32) | (long)rand.Next();
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Span<bool> unpacks = stackalloc bool[64];
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value.Unpack(unpacks);
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Assert.AreEqual(value, unpacks.PackInt64());
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}
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}
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103
X10D/src/Core/IntrinsicExtensions.cs
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103
X10D/src/Core/IntrinsicExtensions.cs
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@ -0,0 +1,103 @@
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#if NETCOREAPP3_0_OR_GREATER
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using System;
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using System.Collections.Generic;
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using System.Linq;
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using System.Text;
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using System.Threading.Tasks;
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using System.Runtime.Intrinsics;
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using System.Runtime.Intrinsics.X86;
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using System.Runtime.Intrinsics.Arm;
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using System.Diagnostics.Contracts;
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using System.Runtime.CompilerServices;
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using System.Numerics;
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namespace X10D.Core;
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/// <summary>
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/// Extension methods for SIMD vectors, namely <see cref="Vector64{T}"/>, <see cref="Vector128{T}"/> and <see cref="Vector256{T}"/>.
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/// </summary>
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public static class IntrinsicExtensions
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{
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/// <summary>
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/// Correcting <see cref="Vector64{T}"/> of <see langword="byte"/> into standard boolean values.
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/// </summary>
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/// <param name="vector">Vector of byte to correct.</param>
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/// <returns>Corrected boolean in form of <see cref="Vector64{T}"/> of bytes.</returns>
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/// <remarks>This method will ensure that every value can only be 0 or 1. Values of 0 will be kept, and others will be set to 1.</remarks>
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[Pure]
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[MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)]
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public static Vector64<byte> CorrectBoolean(this Vector64<byte> vector)
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{
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if (AdvSimd.IsSupported)
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{
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// Haven't tested since March 6th 2023 (Reason: Unavailable hardware).
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var cmp = AdvSimd.CompareEqual(vector, Vector64<byte>.Zero);
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var result = AdvSimd.BitwiseSelect(cmp, vector, Vector64<byte>.Zero);
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return result;
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}
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if (Sse.IsSupported)
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{
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throw new PlatformNotSupportedException("Cannot correct boolean of Vector64<byte> on SSE intrinsic set.");
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}
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throw new PlatformNotSupportedException("Unknown Intrinsic platform.");
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}
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/// <summary>
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/// Correcting <see cref="Vector128{T}"/> of <see langword="byte"/> into standard boolean values.
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/// </summary>
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/// <param name="vector">Vector of byte to correct.</param>
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/// <returns>Corrected boolean in form of <see cref="Vector128{T}"/> of bytes.</returns>
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/// <remarks>This method will ensure that every values can only be either 0 to represent <see langword="false"/> and 1 to represent <see langword="true"/>. Values of 0 will be kept, and others will be mapped back to 1.</remarks>
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[Pure]
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[MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)]
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public static Vector128<byte> CorrectBoolean(this Vector128<byte> vector)
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{
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if (Sse2.IsSupported)
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{
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var cmp = Sse2.CompareEqual(vector, Vector128<byte>.Zero);
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var result = Sse2.AndNot(cmp, Vector128.Create((byte)1));
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return result;
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}
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else if (AdvSimd.IsSupported)
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{
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// Haven't tested since March 6th 2023 (Reason: Unavailable hardware).
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var cmp = AdvSimd.CompareEqual(vector, Vector128<byte>.Zero);
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var result = AdvSimd.BitwiseSelect(cmp, vector, Vector128<byte>.Zero);
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return result;
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}
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throw new PlatformNotSupportedException("Unknown Intrinsic platform.");
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}
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/// <summary>
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/// Correcting <see cref="Vector256{T}"/> of <see langword="byte"/> into standard boolean values.
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/// </summary>
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/// <param name="vector">Vector of byte to correct.</param>
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/// <returns>Corrected boolean in form of <see cref="Vector256{T}"/> of bytes.</returns>
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/// <remarks>This method will ensure that every value can only be 0 or 1. Values of 0 will be kept, and others will be set to 1.</remarks>
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[Pure]
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[MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)]
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public static Vector256<byte> CorrectBoolean(this Vector256<byte> vector)
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{
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if (Avx2.IsSupported)
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{
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var cmp = Avx2.CompareEqual(vector, Vector256<byte>.Zero);
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var result = Avx2.AndNot(cmp, Vector256.Create((byte)1));
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return result;
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}
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if (AdvSimd.IsSupported)
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{
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throw new PlatformNotSupportedException("Cannot correct boolean of Vector256<byte> on ARM intrinsic set.");
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}
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throw new PlatformNotSupportedException("Unknown Intrinsic platform.");
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}
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}
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#endif
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222
X10D/src/Core/IntrinsicUtility.cs
Normal file
222
X10D/src/Core/IntrinsicUtility.cs
Normal file
@ -0,0 +1,222 @@
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#if NETCOREAPP3_0_OR_GREATER
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using System.Diagnostics.CodeAnalysis;
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using System.Diagnostics.Contracts;
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using System.Runtime.CompilerServices;
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using System.Runtime.Intrinsics;
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using System.Runtime.Intrinsics.Arm;
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using System.Runtime.Intrinsics.X86;
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namespace X10D.Core;
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/// <summary>
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/// Provides utility methods for SIMD vector that is currently missing on common hardware instruction set.
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/// </summary>
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public static class IntrinsicUtility
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{
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/// <summary>
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/// <br>Multiply packed 64-bit unsigned integer elements in a and b and truncate the results to 64-bit integer.</br>
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/// <br>Operation:</br>
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/// <code>
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/// dest[0] = lhs[0] * rhs[0];
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/// dest[1] = lhs[1] * rhs[1];
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/// </code>
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/// </summary>
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/// <param name="lhs">Left vector.</param>
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/// <param name="rhs">Right vector.</param>
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/// <returns></returns>
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/// <remarks>API avaliable on SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, ARM NEON (untested) hardwares.</remarks>
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[Pure]
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[CLSCompliant(false)]
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[MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)]
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public static Vector128<ulong> Multiply(Vector128<ulong> lhs, Vector128<ulong> rhs)
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{
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if (Sse2.IsSupported)
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{
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// https://stackoverflow.com/questions/17863411/sse-multiplication-of-2-64-bit-integers
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Vector128<ulong> ac = Sse2.Multiply(lhs.AsUInt32(), rhs.AsUInt32());
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Vector128<uint> b = Sse2.ShiftRightLogical(lhs, 32).AsUInt32();
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Vector128<ulong> bc = Sse2.Multiply(b, rhs.AsUInt32());
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Vector128<uint> d = Sse2.ShiftRightLogical(rhs, 32).AsUInt32();
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Vector128<ulong> ad = Sse2.Multiply(lhs.AsUInt32(), d);
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Vector128<ulong> high = Sse2.Add(bc, ad);
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high = Sse2.ShiftLeftLogical(high, 32);
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return Sse2.Add(high, ac);
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}
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else if (AdvSimd.IsSupported)
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{
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// https://stackoverflow.com/questions/60236627/facing-problem-in-implementing-multiplication-of-64-bit-variables-using-arm-neon
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// Hasn't been tested since March 7th 2023 (Reason: Unavailable hardware)
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var a = AdvSimd.ExtractNarrowingLower(lhs);
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var b = AdvSimd.ExtractNarrowingLower(rhs);
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var mul = AdvSimd.Multiply(rhs.AsUInt32(), AdvSimd.ReverseElement32(lhs).AsUInt32());
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return AdvSimd.MultiplyWideningLowerAndAdd(AdvSimd.ShiftLeftLogical(mul.AsUInt64(), 32), a, b);
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}
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throw new PlatformNotSupportedException("Unsupported SIMD platform.");
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}
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/// <summary>
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/// <br>Multiply packed 64-bit unsigned integer elements in a and b and truncate the results to 64-bit integer.</br>
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/// <br>Operation:</br>
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/// <code>
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/// dest[0] = lhs[0] * rhs[0];
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/// dest[1] = lhs[1] * rhs[1];
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/// dest[2] = lhs[2] * rhs[2];
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/// dest[3] = lhs[3] * rhs[3];
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/// </code>
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/// </summary>
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/// <param name="lhs">Left vector.</param>
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/// <param name="rhs">Right vector.</param>
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/// <returns></returns>
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/// <remarks>API avaliable on AVX2 hardware.</remarks>
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[Pure]
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[CLSCompliant(false)]
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[MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)]
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public static Vector256<ulong> Multiply(Vector256<ulong> lhs, Vector256<ulong> rhs)
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{
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if (Avx2.IsSupported)
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{
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// https://stackoverflow.com/questions/17863411/sse-multiplication-of-2-64-bit-integers
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Vector256<ulong> ac = Avx2.Multiply(lhs.AsUInt32(), rhs.AsUInt32());
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Vector256<uint> b = Avx2.ShiftRightLogical(lhs, 32).AsUInt32();
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Vector256<ulong> bc = Avx2.Multiply(b, rhs.AsUInt32());
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Vector256<uint> d = Avx2.ShiftRightLogical(rhs, 32).AsUInt32();
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Vector256<ulong> ad = Avx2.Multiply(lhs.AsUInt32(), d);
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Vector256<ulong> high = Avx2.Add(bc, ad);
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high = Avx2.ShiftLeftLogical(high, 32);
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return Avx2.Add(high, ac);
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}
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throw new PlatformNotSupportedException("Unsupported SIMD platform.");
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}
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/// <summary>
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/// <para>Multiply packed 64-bit signed integer elements in a and b and truncate the results to 64-bit integer.</para>
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/// <para>Operation:</para>
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/// <code>
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/// dest[0] = lhs[0] * rhs[0];
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/// dest[1] = lhs[1] * rhs[1];
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/// </code>
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/// </summary>
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/// <param name="lhs">Left vector.</param>
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/// <param name="rhs">Right vector.</param>
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/// <returns></returns>
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||||
/// <remarks>API avaliable on SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, ARM NEON (untested) hardwares.</remarks>
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[Pure]
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[MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)]
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public static Vector128<long> Multiply(Vector128<long> lhs, Vector128<long> rhs)
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{
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return Multiply(lhs.AsUInt64(), rhs.AsUInt64()).AsInt64();
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}
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||||
|
||||
/// <summary>
|
||||
/// <br>Multiply packed 64-bit signed integer elements in a and b and truncate the results to 64-bit integer.</br>
|
||||
/// <br>Operation:</br>
|
||||
/// <code>
|
||||
/// dest[0] = lhs[0] * rhs[0];
|
||||
/// dest[1] = lhs[1] * rhs[1];
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/// dest[2] = lhs[2] * rhs[2];
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/// dest[3] = lhs[3] * rhs[3];
|
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/// </code>
|
||||
/// </summary>
|
||||
/// <param name="lhs">Left vector.</param>
|
||||
/// <param name="rhs">Right vector.</param>
|
||||
/// <returns></returns>
|
||||
/// <remarks>API avaliable on AVX2 hardware.</remarks>
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||||
[Pure]
|
||||
[MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)]
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||||
public static Vector256<long> Multiply(Vector256<long> lhs, Vector256<long> rhs)
|
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{
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return Multiply(lhs.AsUInt64(), rhs.AsUInt64()).AsInt64();
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||||
}
|
||||
|
||||
/// <summary>
|
||||
/// <para>Horizontally apply OR operation on adjacent pairs of single-precision (32-bit) floating-point elements in lhs and rhs.</para>
|
||||
/// <para>Operation:</para>
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||||
/// <code>
|
||||
/// dest[0] = lhs[0] | lhs[1];
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||||
/// dest[1] = lhs[2] | lhs[3];
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||||
/// dest[2] = rhs[0] | rhs[1];
|
||||
/// dest[3] = rhs[2] | rhs[3];
|
||||
/// </code>
|
||||
/// </summary>
|
||||
/// <param name="lhs">Left vector.</param>
|
||||
/// <param name="rhs">Right vector.</param>
|
||||
/// <returns></returns>
|
||||
/// <remarks>API avaliable on SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, ARM64 NEON (untested) hardwares.</remarks>
|
||||
[Pure]
|
||||
[MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)]
|
||||
public static Vector128<float> HorizontalOr(Vector128<float> lhs, Vector128<float> rhs)
|
||||
{
|
||||
if (Sse.IsSupported)
|
||||
{
|
||||
var s1 = Sse.Shuffle(lhs, rhs, 0b10_00_10_00);
|
||||
var s2 = Sse.Shuffle(lhs, rhs, 0b11_01_11_01);
|
||||
|
||||
return Sse.Or(s1, s2);
|
||||
}
|
||||
else if (AdvSimd.Arm64.IsSupported)
|
||||
{
|
||||
// Hasn't been tested since March 7th 2023 (Reason: Unavailable hardware).
|
||||
var s1 = AdvSimd.Arm64.UnzipEven(lhs, rhs);
|
||||
var s2 = AdvSimd.Arm64.UnzipOdd(lhs, rhs);
|
||||
|
||||
return AdvSimd.Or(s1, s2);
|
||||
}
|
||||
|
||||
throw new PlatformNotSupportedException("Unsupported SIMD platform.");
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// <para>Horizontally apply OR operation on adjacent pairs of 32-bit integer elements in lhs and rhs.</para>
|
||||
/// <para>Operation:</para>
|
||||
/// <code>
|
||||
/// dest[0] = lhs[0] | lhs[1];
|
||||
/// dest[1] = lhs[2] | lhs[3];
|
||||
/// dest[2] = rhs[0] | rhs[1];
|
||||
/// dest[3] = rhs[2] | rhs[3];
|
||||
/// </code>
|
||||
/// </summary>
|
||||
/// <param name="lhs">Left vector.</param>
|
||||
/// <param name="rhs">Right vector.</param>
|
||||
/// <returns></returns>
|
||||
/// <remarks>API avaliable on SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, ARM64 NEON (untested) hardwares.</remarks>
|
||||
[Pure]
|
||||
[MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)]
|
||||
public static Vector128<int> HorizontalOr(Vector128<int> lhs, Vector128<int> rhs)
|
||||
{
|
||||
return HorizontalOr(lhs.AsSingle(), rhs.AsSingle()).AsInt32();
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// <para>Horizontally apply OR operation on adjacent pairs of 32-bit unsigned integer elements in lhs and rhs.</para>
|
||||
/// <para>Operation:</para>
|
||||
/// <code>
|
||||
/// dest[0] = lhs[0] | lhs[1];
|
||||
/// dest[1] = lhs[2] | lhs[3];
|
||||
/// dest[2] = rhs[0] | rhs[1];
|
||||
/// dest[3] = rhs[2] | rhs[3];
|
||||
/// </code>
|
||||
/// </summary>
|
||||
/// <param name="lhs">Left vector.</param>
|
||||
/// <param name="rhs">Right vector.</param>
|
||||
/// <returns></returns>
|
||||
/// <remarks>API avaliable on SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, ARM64 NEON (untested) hardwares.</remarks>
|
||||
[Pure]
|
||||
[MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)]
|
||||
[CLSCompliant(false)]
|
||||
public static Vector128<uint> HorizontalOr(Vector128<uint> lhs, Vector128<uint> rhs)
|
||||
{
|
||||
return HorizontalOr(lhs.AsSingle(), rhs.AsSingle()).AsUInt32();
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user